Vias around CPW to supress resonance modes on PCB
I am designing a PCB to interface with a smaller chip that has CPW-based RF circuits operating at 5-10 GHz. The PCB will have SMP connectors at the edge, with CPWs routed to the center where they will be wire bonded to the CPWs on the chip. It is a single layer PCB with a metal-plated backplane. I have attached an example image.
In my field of research, it is common practice to add a grid of vias connecting the ground planes on the top layer with the backplane. This has two main purposes: 1 - These are devices that operate at cryogenic temperatures, and we need a thermal connection between the top layer of the PCB and the backplane, which is mounted on the cold metal finger; 2 - We want to supress unwanted resonance modes from the larger volume of dielectric that constitutes the PCB.
My RF intuition says that we want to avoid vias as much as possible because of the extra inductance, so when I see these grids of vias on CPWs I cringe a bit. I'm trying to design my own PCB, and I was wondering if this practice of adding grids of vias to supress unwanted modes is common, and whether anyone knows any references to help me design this more effectively. I have a feeling that I can get away with a much lesser dense grid than show in the picture, but I'm not sure how to design it.
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